1. Field of the Invention
The present invention relates to analog compensation circuitry for digital circuits, and in particular, to analog compensation circuits and methods for reducing DC offset voltages.
2. Description of the Related Art
Referring to FIG. 1, conventional high-speed analog adaptive equalizers, such as the three-tap feed-forward equalizer (FFE) illustrated here, use analog multipliers in performing least-mean-square (LMS) adaptation. The incoming digital data signal s0(t) at lead 11 is sequentially delayed by delay elements 12a, 12b (e.g., each imparting a delay equivalent to one data symbol), thereby producing two sequentially delayed signals s1(t) and s2(t) at leads 13a and 13b, respectively. The original s0(t) and delayed s1(t), s2(t) signals are multiplied with coefficient signals C0, C1 and C2 provided via leads 25a, 25b and 25c, respectively, in signal multipliers 14a, 14b, 14c. The resulting product signals are conveyed via leads 15a, 15b and 15c and summed in a summing circuit 16. The resulting sum signal is conveyed via lead 17 and sliced by a signal slicer 18 and subtracted from the sliced signal provided at lead 19 in a differential summing circuit 20. The resulting signal on lead 21 is an error signal e(t) representing the error, or difference, between the pre-slice signal on lead 17 and post-slice signal on lead 19. This error signal e(t) is multiplied in analog mixing circuits 22a, 22b, 22c with the original s0(t) and delayed s1(t), s2(t) data signals. The resulting product signals are conveyed via leads 23a, 23b and 23c and filtered with low-pass filters 24a, 24b, 24c to produce the coefficient signals C0, C1 and C2 on leads 25a, 25b and 25c, respectively.
A common problem with such circuits, particularly in an integrated circuit (IC) implementation, is that of DC offset voltages. For example, the error signal e(t), as well as the data signals s0(t), s1(t), s2(t), should have zero mean values, i.e., zero volts DC, and the analog multiplier output signals on leads 23a, 23b and 23c should be exactly proportional to the product of the error signal e(t) and the respective data signals s0(t), s1(t), s2(t). However, particularly for deep-submicron analog integrated circuits using complementary metal oxide semiconductor (CMOS) technology, this is not true.